Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
Presently, a final circuit design (referenced herein as the top-level design) for a PLD may include many logic pieces (referenced herein as modules). All of the logic pieces may be implemented at one time to form a full implementation for a target PLD. Alternatively, each module may be designed and implemented separately. Implemented modules are then combined to form a full implementation for a target PLD. In addition, some PLDs support dynamic reconfiguration while active. That is, some PLDs have the ability to re-program a portion of the PLD while the rest of the PLD continues to operate normally.
In modular design flows, areas in the floorplan of the PLD are specified for module implementation. Conventionally, the areas are specified by defining a rectangular area on the floorplan of the PLD where the logic and routing of the module is to be implemented. Specifying such areas (referred to as “area constraints”) may be accomplished by manual layout and/or utilizing floorplanning tools. This process has worked fairly well in the past, but has begun to yield sub-optimal use in newer PLD architectures.
Present FPGAs, for example, now incorporate special purpose logic within the fabric, such as block random access memories (BRAMs), digital signal processors (DSPs), first-in-first-out memories (FIFOs), microprocessors, and the like, as well as a whole set of specific function cores. Such special purpose logic may exist in columns throughout the fabric of the device, or may just exist by creating a “hole” in the fabric of the device. A “hole” is defined as some logic that replaces a piece of one or more columns and/or rows of the general fabric logic (e.g., CLBs). As such, it is becoming difficult to define a rectangular area that contains logic that a module implementation requires without encompassing special purpose logic or other general purpose logic interspersed in the fabric that the module does not need. Accordingly, there exists a need in the art for an improved method and apparatus for modular circuit design for PLDs having special purpose logic in the fabric.